The present invention relates to three state gates or drivers, and more specifically to the testing of such three state drivers (TSD) and associated circuit means.
A TSD is a binary gate that includes a data input, a data output, and an enable input. When the TSD is enabled, its output is in a low impedance state, and the binary signal then present on its input appears at its output. Thus an enabled TSD's output can be at one of two logic states, i.e. a binary "1" or a binary "0", depending upon the state of the input signal. The enabled state of a TSD is called its active state.
When the TSD is not enabled, its output is in a high impedance state (H state). In the H state, the TSD effectively disconnects itself from the circuit to which it is connected in its active state, to drive with a logical "1" or a logical "0". In the H state, the output of the TSD must appear as an open circuit, neither attempting to charge nor discharge the circuit to which its output is physically connected (sometimes called the fanout of the bus).
A common use of TSDs is to selectively connect only one of a number of logical devices to a bus, net or wire that is shared by all of the logical devices. More specifically, the one device that is to be connected to the bus has its TSD enabled, as the TSDs of all other devices are disabled. Since all disabled TSDs are, or should be, in their high impedance state, the bus receives or transmits binary data only from the one logical device.
The H state of TSDs has challenged skilled practitioners to provide adequate and reliable means to test the operation of TSDs within the framework of the logic-oriented systems to which the TSDs are connected. Typically, it was necessary to consider this H state as a "don't care" or "unknown" state during testing. Thus, this condition of the embedded TSD busses was generally not tested in the prior art, and it was difficult for the logical designer to verify that a logic design was operating or would operate as intended.
The present invention relates to the testing of embedded three state logic circuitry.
This invention finds utility where a three state bus is embedded on a chip, as well as in other embedded arrangements, such as, for example, where three state busses, while not embedded in an integrated circuit chip per se, connect from one chip to another chip on a multiple chip carrier, where the busses are not brought out of, or off of, the carrier for testing.
Arrangements for testing integrated circuits are known in the art.
For example, U.S. Pat. No. 4,528,505 describes an arrangement whereby a test transistor may be provided on every IC, and wherein the threshold voltage of this transistor is calculated, based upon its measured gate-to-source voltage for two different drain-to-source current values. In this way, ICs are screened to determine which are likely to fail at high and low temperatures, due to threshold voltage sensitivities.
Arrangements for testing busses are also known. Some examples are as follows.
U.S. Pat. No. 3,849,726 discloses an arrangement for testing an interface line. In the line-drive-test mode of operation, a binary "1" or "0" signal of programmed value is applied to the interface line, and thereby to the unit under test. In the line-response-test mode of operation, a programmable loading circuit sets up loading conditions for the interface line that are necessary to evaluate the quality of the unit under test. In this response-test mode, a comparator circuit is provided to evaluate an expected logical "1" or logical "0" received from the interface line, by comparing the magnitude of these logical interface line signals to reference values. U.S. Pat. No. 4,236,246 teaches an arrangement for detecting and locating faults in electronic components, such as tri-state components, that are interconnected by nodes. The nodes are driven by voltage signals that corresponded to the high and low logic states of the components, and to a third state that should exist when the nodes are disconnected from the components. Comparators operate to compare (1) the mode's actual response to these signals, to (2) signals which represent the mode's expected response to these signals. An error signal is generated when the node's actual response does not compare to the expected response.
U.S. Pat. No. 4,459,693 describes an arrangement for diagnosing failure on tri-state bus nodes. If failure is detected, the component causing the failure is identified. More specifically, all components connected to the bus nodes are first disabled. High and low reference voltages are then connected to each bus node through resistors. Measurements are made to determine if the mode voltage can be controlled by these voltages and these resistors. If "yes", normal component test proceeds. If "no", a procedure to locate the failing component begins. In this failure locating procedure, the components are sequentially enabled, one by one, to locate the component whose enablement does not appreciably change the test measurement. That component is then identified as the failing component.
U.S. Pat. No. 4,490,673 describes an arrangement for testing an integrated circuit containing a tri-state driver, where the driver and its control signal generator (i.e. the network whose output determines whether the driver will operate in its active or in its high impedance mode of operation) are on the same integrated circuit chip. In this arrangement, the driver is first forced to its high impedance state, and its output is checked to assure that the driver has properly reached this state. The driver is then forced to its active state, independent of the output of the control signal generator. A test pattern is then applied to the control signal generator. Since the driver is now held active, the driver's output is at all times a measure of the response of the control signal generator to the test pattern.
While these arrangements have provided some measure of reliable testing, they did not provide a construction and arrangement that enabled reliable testing of embedded three state busses, or reliable testing of the high impedance state of three state busses.